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February 1996
NDS9948 Dual P-Channel Enhancement Mode Field Effect Transistor
General Description
These P-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as notebook computer power management and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.
Features
-2.3A, -60V. RDS(ON) = 0.25 @ VGS = -10V. High density cell design for low RDS(ON). High power and current handling capability in a widely used surface mount package. Dual MOSFET in surface mount package.
______________________________________________________________________________
5
4 3 2
1
6
7 8
Absolute Maximum Ratings
Symbol VDSS VGSS ID Parameter Drain-Source Voltage Gate-Source Voltage Drain Current
T A = 25C unless otherwise noted
NDS9948 -60 20
(Note 1a)
Units V V A
- Continuous TA = 25C - Pulsed - Continuous TA = 25C TA = 70C
2.3 10
(Note 1a)
1.8 2 W
PD
Power Dissipation for Dual Operation Power Dissipation for Single Operation
(Note 1a) (Note 1b) (Note 1c)
1.6 1 0.9 -55 to 150 C
TJ,TSTG
Operating and Storage Temperature Range
THERMAL CHARACTERISTICS RJA RJC Thermal Resistance, Junction-to-Ambient Thermal Resistance, Junction-to-Case
(Note 1a) (Note 1)
78 40
C/W C/W
(c) 1997 Fairchild Semiconductor Corporation
NDS9948.SAM
Electrical Characteristics (TA = 25C unless otherwise noted)
Symbol BVDSS IDSS IGSSF IGSSR VGS(th) RDS(ON) Parameter Drain-Source Breakdown Voltage Zero Gate Voltage Drain Current Conditions VGS = 0 V, ID = -250 A VDS = -40 V, VGS = 0 V TJ = 55C Gate - Body Leakage, Forward Gate - Body Leakage, Reverse Gate Threshold Voltage Static Drain-Source On-Resistance VGS = 20 V, VDS = 0 V VGS = -20V, VDS= 0 V VDS = VGS, ID = -250 A TJ =125C VGS = -10 V, ID = -2.3 A TJ =125C VGS = -4.5 V, ID = -1.6 A ID(on) gFS Ciss Coss Crss tD(on) tr tD(off) tf Qg Qgs Qgd On-State Drain Current Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Turn - On Delay Time Turn - On Rise Time Turn - Off Delay Time Turn - Off Fall Time Total Gate Charge Gate-Source Charge Gate-Drain Charge VDS = -30 V, ID = -2.3 A, VGS = -10 V VDD = -30 V, ID = -1 A, VGEN = -10 V, RGEN = 6 VGS = -10 V, VDS = -5 V VDS = -15 V, ID = -2.3 A VDS = -25 V, VGS = 0 V, f = 1.0 MHz -10 3.5 570 140 40 8 20 20 5 16 2 4 15 40 40 20 25 5 8 -1 -0.8 -2.4 -2 0.21 0.3 0.36 Min -60 -2 -25 100 -100 -3 -2.6 0.25 0.4 0.5 A S pF pF pF ns ns ns ns nC nC nC Typ Max Units V A A nA nA V OFF CHARACTERISTICS
ON CHARACTERISTICS (Note 2)
DYNAMIC CHARACTERISTICS
SWITCHING CHARACTERISTICS (Note 2)
NDS9948.SAM
Electrical Characteristics (TA = 25C unless otherwise noted)
Symbol IS VSD
Notes: 1. RJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RJC is guaranteed by design while RCA is determined by the user's board design.
Parameter
Conditions
Min
Typ
Max -1.7
Units A V
DRAIN-SOURCE DIODE CHARACTERISTICS AND MAXIMUM RATINGS Maximum Continuous Drain-Source Diode Forward Current Drain-Source Diode Forward Voltage VGS = 0 V, IS = -2.3 A
(Note 2)
-0.98
-1.2
PD(t) =
R J A (t)
TJ
-TA
=
TJ
-TA
R J C CA +R (t)
= I 2 (t) x RDS(ON ) D
TJ
Typical RJA for single device operation using the board layouts shown below on 4.5"x5" FR-4 PCB in a still air environment: a. 78oC/W when mounted on a 0.5 in2 pad of 2oz cpperr. b. 125oC/W when mounted on a 0.02 in2 pad of 2oz cpper. c. 135oC/W when mounted on a 0.003 in2 pad of 2oz cpper.
1a
1b
1c
Scale 1 : 1 on letter size paper
2. Pulse Test: Pulse Width < 300s, Duty Cycle < 2.0%.
NDS9948.SAM
Typical Electrical Characteristics
-12
3
V
I D , DRAIN-SOURCE CURRENT (A)
GS
= -10V
-8.0
-7.0
R DS(on), NORMALIZED
V
DRAIN-SOURCE ON-RESISTANCE
GS
= -4.0V
-6.0
-9
-4.5 -5.0 -5.5
2.5
-5.5
2
-6
-5.0 -4.5
-6.0
1.5
-7.0 -8.0
-3
-4.0 -3.5
0 0 -1 -2 -3 -4 VDS , DRAIN-SOURCE VOLTAGE (V) -5 -6
1
-10
0.5
0
-3
-6 -9 ID , DRAIN CURRENT (A)
-12
-15
Figure 1. On-Region Characteristics.
Figure 2. On-Resistance Variation with Gate Voltage and Drain Current.
1.6
3
DRAIN-SOURCE ON-RESISTANCE
I D = -2.3A
DRAIN-SOURCE ON-RESISTANCE 1.4
V GS = -10 V
V GS = -10V
R DS(ON), NORMALIZED
R DS(ON), NORMALIZED
2
1.2
TJ = 125C
1
25C
1
-55C
0.8
0.6 -50
-25
0 25 50 75 100 T , JUNCTION TEMPERATURE (C)
J
125
150
0
0
-3 I
D
-6
-9
-12
-15
, DRAIN CURRENT (A)
Figure 3. On-Resistance Variation with Temperature.
Figure 4. On-Resistance Variation with Drain Current and Temperature.
-10
1.2
25C
GATE-SOURCE THRESHOLD VOLTAGE (V)
V DS = -10V
-8 ID , DRAIN CURRENT (A)
T = -55C J
125C
1.1
V DS = V GS I D = -250A
-6
V th, NORMALIZED
1
-4
0.9
-2
0.8
0
-2
-3 V
GS
-4 -5 -6 , GATE TO SOURCE VOLTAGE (V)
-7
0.7 -50
-25
0 25 50 75 100 T J , JUNCTION TEMPERATURE (C)
125
150
Figure 5. Drain Current Variation with Gate Voltage and Temperature.
Figure 6. Gate Threshold Variation with Temperature.
NDS9948.SAM
Typical Electrical Characteristics (continued)
1.15
10
DRAIN-SOURCE BREAKDOWN VOLTAGE (V)
I D = -250A
1.1
5 -I S , REVERSE DRAIN CURRENT (A)
V GS = 0V
BV DSS, NORMALIZED
1 0.5
125C
1.05
25C T J = -55C
0.1
1
0.95
0.01
0.9 -50
-25
0 T J
25 50 75 100 , JUNCTION TEMPERATURE (C)
125
150
0.001 -0.3
-0.6 V
SD
-0.9
-1.2
-1.5
-1.8
-2.1
, BODY DIODE FORWARD VOLTAGE (V)
Figure 7. Breakdown Voltage Variation with Temperature.
Figure 8. Body Diode Forward Voltage Variation with Current and Temperature.
1000
10
C iss
, GATE-SOURCE VOLTAGE (V) 500 300 200 8
IDS = -2.3A
VDS = -10V
-30V -20V
CAPACITANCE (pF)
C oss
6
100
4
50 30 20 0.1
f = 1 MHz V GS = 0V
0.2 0.5 1 2 5 10 -V DS , DRAIN TO SOURCE VOLTAGE (V) 20
C rss
-V 50 0 0
GS
2
5
10 Q g , GATE CHARGE (nC)
15
20
Figure 9. Capacitance Characteristics.
Figure 10. Gate Charge Characteristics.
-VDD V IN
D
t on
RL V OUT
DUT
t d(on)
tr
90%
t d(off)
toff tf
90%
VGS
VOUT
R GEN
10%
10% 90%
G
S
V IN
10%
50%
50%
INVERTED
PULSE WIDTH
Figure 11. Switching Test Circui.t
Figure 12. Switching Waveforms.
NDS9948.SAM
Typical Electrical Characteristics (continued)
6 , TRANSCONDUCTANCE (SIEMENS)
20
V DS = -15V
T = -55C J
-I D, DRAIN CURRENT (A)
10 5
I )L T MI
10 1m
S( ON
0u
s
s
25C
4
2 1 0.5
RD
10 10 1s
DC
m
s
125C
0m
s
2
V
0.1 0.05
GS
= -10V
SINGLE PULSE R J A = 100 o C/W T A = 25C
0.5 -V
DS
g
FS
0
0
-2
-4 -6 I D , DRAIN CURRENT (A)
-8
-10
0.01 0.1
0.2
1
2
5
10
60
100
, DRAIN-SOURCE VOLTAGE (V)
Figure 13. Transconductance Variation with Drain Current and Temperature.
Figure 14. Maximum Safe Operating Area.
1 0 .5
r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE
D = 0.5 0.2 0.1 0.05 0.02 0.01 Single Pulse P(pk)
0 .2 0 .1 0 .0 5 0 .0 2 0 .0 1 0 .0 0 5 0 .0 0 2 0 .0 0 1 0 .0001
R JA (t) = r(t) * R JA R JA = See Note 1c
t1 TJ - T
A
t2
= P * R JA (t) Duty Cycle, D = t 1 / t 2 0 .001 0 .0 1 0 .1 1 10 100 300
t 1 , TIME (sec)
Figure 15. Transient Thermal Response Curve.
Note: Thermal characterization performed using the conditions described in note 1c. Transient thermal response will change depending on the circuit board design.
NDS9948.SAM
SO-8 Tape and Reel Data and Package Dimensions
SOIC(8lds) Packaging Configuration: Figure 1.0
Packaging Description:
EL ECT ROST AT IC SEN SIT IVE DEVICES
DO NO T SHI P OR STO RE N EAR ST RO NG EL ECT ROST AT IC EL ECT RO M AGN ETI C, M AG NET IC O R R ADIO ACT IVE FI ELD S
TNR D ATE PT NUMB ER PEEL STREN GTH MIN ___ __ ____ __ ___gms MAX ___ ___ ___ ___ _ gms
Antistatic Cover Tape
ESD Label
SOIC-8 parts are shipped in tape. The carrier tape is made from a dissipative (carbon filled) polycarbonate resin. The cover tape is a multilayer film (Heat Activated Adhesive in nature) primarily composed of polyester film, adhesive layer, sealant, and anti-static sprayed agent. These reeled parts in standard option are shipped with 2,500 units per 13" or 330cm diameter reel. The reels are dark blue in color and is made of polystyrene plastic (antistatic coated). Other option comes in 500 units per 7" or 177cm diameter reel. This and some other options are further described in the Packaging Information table. These full reels are individually barcode labeled and placed inside a standard intermediate box (illustrated in figure 1.0) made of recyclable corrugated brown paper. One box contains two reels maximum. And these boxes are placed inside a barcode labeled shipping box which comes in different sizes depending on the number of parts shipped.
Static Dissipative Embossed Carrier Tape
F63TNR Label Customized Label
F852 NDS 9959 F852 NDS 9959 F852 NDS 9959 F852 NDS 9959
SOIC (8lds) Packaging Information Packaging Option Packaging type Qty per Reel/Tube/Bag Reel Size Box Dimension (mm) Max qty per Box Weight per unit (gm) Weight per Reel (kg) Note/Comments Standard (no flow code) TNR 2,500 13" Dia 343x64x343 5,000 0.0774 0.6060 L86Z Rail/Tube 95 530x130x83 30,000 0.0774 F011 TNR 4,000 13" Dia 343x64x343 8,000 0.0774 0.9696 D84Z TNR 500 7" Dia 184x187x47 1,000 0.0774 0.1182
F852 NDS 9959
Pin 1
SOIC-8 Unit Orientation
343mm x 342mm x 64mm Standard Intermediate box ESD Label F63TNR Label sample
LOT: CBVK741B019 FSID: FDS9953A QTY: 2500 SPEC:
F63TNLabel F63TN Label ESD Label
(F63TNR)3
D/C1: D9842 D/C2:
QTY1: QTY2:
SPEC REV: CPN: N/F: F
SOIC(8lds) Tape Leader and Trailer Configuration: Figure 2.0
Carrier Tape Cover Tape
Components Trailer Tape 640mm minimum or 80 empty pockets Leader Tape 1680mm minimum or 210 empty pockets
July 1999, Rev. B
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC(8lds) Embossed Carrier Tape Configuration: Figure 3.0
T E1
P0
D0
F K0 Wc B0 E2 W
Tc A0 P1 D1
User Direction of Feed
Dimensions are in millimeter Pkg type SOIC(8lds) (12mm)
A0
6.50 +/-0.10
B0
5.30 +/-0.10
W
12.0 +/-0.3
D0
1.55 +/-0.05
D1
1.60 +/-0.10
E1
1.75 +/-0.10
E2
10.25 min
F
5.50 +/-0.05
P1
8.0 +/-0.1
P0
4.0 +/-0.1
K0
2.1 +/-0.10
T
0.450 +/0.150
Wc
9.2 +/-0.3
Tc
0.06 +/-0.02
Notes: A0, B0, and K0 dimensions are determined with respect to the EIA/Jedec RS-481 rotational and lateral movement requirements (see sketches A, B, and C).
20 deg maximum Typical component cavity center line
0.5mm maximum
B0 20 deg maximum component rotation
0.5mm maximum
Sketch A (Side or Front Sectional View)
Component Rotation
A0 Sketch B (Top View)
Typical component center line
Sketch C (Top View)
Component lateral movement
SOIC(8lds) Reel Configuration: Figure 4.0
Component Rotation
W1 Measured at Hub
Dim A Max
Dim A max
Dim N
See detail AA
7" Diameter Option
B Min Dim C See detail AA W3
Dim D min
13" Diameter Option
W2 max Measured at Hub DETAIL AA
Dimensions are in inches and millimeters
Tape Size
12mm
Reel Option
7" Dia
Dim A
7.00 177.8 13.00 330
Dim B
0.059 1.5 0.059 1.5
Dim C
512 +0.020/-0.008 13 +0.5/-0.2 512 +0.020/-0.008 13 +0.5/-0.2
Dim D
0.795 20.2 0.795 20.2
Dim N
2.165 55 7.00 178
Dim W1
0.488 +0.078/-0.000 12.4 +2/0 0.488 +0.078/-0.000 12.4 +2/0
Dim W2
0.724 18.4 0.724 18.4
Dim W3 (LSL-USL)
0.469 - 0.606 11.9 - 15.4 0.469 - 0.606 11.9 - 15.4
12mm
13" Dia
(c) 1998 Fairchild Semiconductor Corporation
July 1999, Rev. B
SO-8 Tape and Reel Data and Package Dimensions, continued
SOIC-8 (FS PKG Code S1)
1:1
Scale 1:1 on letter size paper
Dimensions shown below are in: inches [millimeters]
Part Weight per unit (gram): 0.0774
9
September 1998, Rev. A
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Rev. E

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